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如何使用內(nèi)部校準(zhǔn)寄存器調(diào)整DAC電壓輸出范圍？AD5360是一種采用8 mm×8 mm 外形尺寸56 引腳LFCSP封裝的高集成度16通道串行輸入±10 V電壓輸出16 bit DAC。它提供一種4倍VREF標(biāo)稱輸出電壓范圍，例如，如果某項(xiàng)設(shè)計(jì)需要－8 V～+8 V輸出電壓范圍，這屬于一種非工業(yè)標(biāo)準(zhǔn)4 V參考電壓，它沒有考慮到DAC的零點(diǎn)誤差和滿度誤差，并且可能會(huì)影響輸出電壓范圍。 為了克服這個(gè)問題，該解決方案提供一種高于要求的電壓范圍的可選擇參考電壓，并且使用內(nèi)部增益寄存器（m）和失調(diào)寄存器（c）獨(dú)立調(diào)整每個(gè)通道輸出達(dá)到要求的范圍。
為了給出－8.192 V～＋8.192 V（包括零點(diǎn)誤差和滿度誤差）大約輸出范圍，使用4.096 V參考電壓。
測(cè)量零點(diǎn)電壓和滿度電壓，例如分別為－8.193 V和＋8.195 V
計(jì)算LSB的大小，即8.195 V － (－8.193 V)/65536 = 250 μV。
為了將零點(diǎn)電壓從－8.193 V移動(dòng)到－8 V需要的步距為0.193 V/250 μV = 772 LSB
現(xiàn)在的滿度電壓為8.195 V+0.193 V=+8.388 V。為了從+8.388 V降低到+8 V需要的步距為0.388 V/250 μV = 1552 LSB。
你現(xiàn)在可以將這些數(shù)據(jù)設(shè)置到DAC通道的失調(diào)寄存器（c）和增益寄存器（m）
失調(diào)寄存器的默認(rèn)值為32768。根據(jù)32768 + 772 = 33540，對(duì)給定的－8 V零點(diǎn)電壓重新設(shè)置這個(gè)數(shù)據(jù)。
增益寄存器的默認(rèn)值為65535。根據(jù)35535－1552 = 63983，對(duì)給定的＋8 V零點(diǎn)電壓重新設(shè)置這個(gè)數(shù)據(jù)。
The AD5360/AD5361 contain 16, 16-/14-bit DACs in a single 52-lead LQFP package. It provides buffered voltage outputs with a span four times the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into two groups of eight DACs, and the output range of each group can be independently adjusted by an offset DAC.
The AD5360/AD5361 offer guaranteed operation over a wide supply range with VSS from −4.5 V to −16.5 V and VDD from +8 V to +16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.
The AD5360/AD5361 have a high speed 4-wire serial interface, which is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register.
Each DAC output is amplified and buffered on-chip with respect to an external SIGGND input. The DAC outputs can also be switched to SIGGND via the CLR pin.
主要特性：
16-channel DAC in 52-lead LQFP package
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of −10 V to +10 V
Multiple output spans available
Temperature monitoring function
Channel monitoring multiplexer
GPIO function
System calibration function allowing user-programmable offset and gain
Channel grouping and addressing features
Data error checking feature
SPI-compatible serial interface
2.5 V to 5.5 V digital interface
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
應(yīng)用：
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical line cards
圖1。AD5360功能方框圖
圖2。和Blackfin DSP 的連接圖
66821730(技術(shù)支持)
